W959D8NFYA5I TR

W959D8NFYA 512Mb HyperRAM Table of Contents1. 2. 3. 4. 5. FEATURES .................................................................................................................................................................................. 3 ORDER INFORMATION .............................................................................................................................................................. 3 BALL ASSIGNMENT.................................................................................................................................................................... 4 BALL DESCRIPTIONS ................................................................................................................................................................ 5 BLOCK DIAGRAM ....................................................................................................................................................................... 6 5.1 Function Block Diagram (Single Die) ............................................................................................................................. 6 5.2 Package Block Diagram (Dual Die Package) ................................................................................................................. 7 6. FUNCTIONAL DESCRIPTION ..................................................................................................................................................... 8 6.1 HyperBus ....................................................................................................................................................................... 8 7. HyperBus TRANSACTION DETAILS ......................................................................................................................................... 11 7.1 Command/Address Bit Assignments ............................................................................................................................ 11 7.2 Read Transactions ....................................................................................................................................................... 14 7.3 Write Transactions (Memory Array Write) .................................................................................................................... 15 7.4 Write Transactions without Initial Latency (Register Write) .......................................................................................... 16 8. MEMORY SPACE ...................................................................................................................................................................... 17 8.1 HyperBus Memory Space addressing.......................................................................................................................... 17 8.1.1 Density and Row Boundaries ......................................................................................................................... 17 9. REGISTER SPACE ................................................................................................................................................................... 18 9.1 HyperBus Register Addressing .................................................................................................................................... 18 9.2 Register Space Access ................................................................................................................................................ 19 9.3 Device Identification Registers ..................................................................................................................................... 20 9.4 Configuration Register 0 .............................................................................................................................................. 20 9.4.1 Wrapped Burst ............................................................................................................................................... 21 9.4.2 Hybrid Burst ................................................................................................................................................... 22 9.4.3 Initial Latency ................................................................................................................................................. 23 9.4.4 Fixed Latency ................................................................................................................................................ 23 9.4.5 Drive Strength ................................................................................................................................................ 23 9.4.6 Deep Power Down ......................................................................................................................................... 23 9.5 Configuration Register 1 .............................................................................................................................................. 24 9.5.1 Master Clock Type ......................................................................................................................................... 24 9.5.2 Partial Array Refresh...................................................................................................................................... 24 9.5.3 Hybrid Sleep .................................................................................................................................................. 25 9.5.4 Distributed Refresh Interval ........................................................................................................................... 25 9.6 Dual-Die-Package (DDP) Application .......................................................................................................................... 26 9.6.1 Die Stack Addressing..................................................................................................................................... 26 9.6.2 Burst Operations - Die Boundary Crossing .................................................................................................... 26 9.6.3 Die number assignment ................................................................................................................................. 26 9.6.4 Latency mode ................................................................................................................................................ 26 9.6.5 IO pad capacitance ........................................................................................................................................ 26 9.6.6 Current consumption...................................................................................................................................... 27 9.6.7 Partial Refresh ............................................................................................................................................... 27 10. INTERFACE STATES ................................................................................................................................................................ 28 10.1 IO condition of interface states..................................................................................................................................... 28 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 1 - W959D8NFYA 10.2 Power Conservation Modes ......................................................................................................................................... 29 10.2.1 Interface Standby ........................................................................................................................................... 29 10.2.2 Active Clock Stop ........................................................................................................................................... 29 10.2.3 Hybrid Sleep .................................................................................................................................................. 29 10.2.4 Deep Power Down ......................................................................................................................................... 30 11. ELECTRICAL SPECIFICATIONS .............................................................................................................................................. 31 11.1 Absolute Maximum Ratings ......................................................................................................................................... 31 11.2 Latch up Characteristics .............................................................................................................................................. 31 11.3 Operating Ranges ........................................................................................................................................................ 31 11.3.1 DC Characteristics ......................................................................................................................................... 31 11.3.2 Operating Temperature Range ...................................................................................................................... 31 11.3.3 ICC Characteristics ........................................................................................................................................ 32 11.3.4 Power-Up Initialization ................................................................................................................................... 33 11.3.5 Power-Down .................................................................................................................................................. 34 11.3.6 Hardware Reset ............................................................................................................................................. 35 11.3.7 Capacitance Characteristics .......................................................................................................................... 36 11.4 Input Signal Overshoot ................................................................................................................................................ 36 12. TIMING SPECIFICATIONS ........................................................................................................................................................ 37 12.1 Key to Switching Waveforms ....................................................................................................................................... 37 12.2 AC Test Conditions ...................................................................................................................................................... 37 12.3 AC Characteristics ....................................................................................................................................................... 38 12.3.1 Read Transactions ......................................................................................................................................... 38 12.3.2 Write Transactions ......................................................................................................................................... 42 12.3.3 Hybrid Sleep Timings ..................................................................................................................................... 44 12.3.4 Deep Power down Timings ............................................................................................................................ 44 13. PACKAGE SPECIFICATION ..................................................................................................................................................... 45 14. REVISION HISTORY ................................................................................................................................................................. 46 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 2 - W959D8NFYA 1. FEATURES • Interface: HyperBus Performance and Power • Power supply: 1.7V~2.0V • Configurable output drive strength • Maximum clock rate: 250MHz • Power Saving Modes • Double-Data Rate (DDR) Up to 500 MB/s – Hybrid Sleep Mode • Clock: – Deep Power Down • Configurable Burst Characteristics – Single ended clock (CK) – Linear burst – Differential clock (CK/CK#) – Wrapped burst lengths: • Chip Select (CS#) • 8-bit data bus (DQ[7:0]) – 16 bytes (8 clocks) • Hardware reset (RESET#) – 32 bytes (16 clocks) • Read-Write Data Strobe (RWDS) – 64 bytes (32 clocks) – 128 bytes (64 clocks) – Bidirectional Data Strobe / Mask – Output at the start of all transactions to indicate refresh latency – Output during read transactions as Read Data Strobe – Input during write transactions as Write Data Mask – Hybrid burst - one wrapped burst followed by linear burst • Array Refresh Modes – Full Array Refresh – Partial Array Refresh • Support package: Dual-Die-Package (DDP), two of 256M bit chip sealed in one 24 balls TFBGA package • Operating temperature range: -40°C ≤ TCASE ≤ 85°C 2. ORDER INFORMATION Part Number VCC/VCCQ I/O Width Package Interface Others W959D8NFYA5I 1.8V 8 24 balls TFBGA, DDP HyperBus 200MHz, -40°C~85°C W959D8NFYA4I 1.8V 8 24 balls TFBGA, DDP HyperBus 250MHz, -40°C~85°C The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 3 - W959D8NFYA 3. BALL ASSIGNMENT 1 2 3 4 5 RFU CS# RESET# RFU CK# CK VSS VCC RFU VSSQ RFU RWDS DQ2 RFU VCCQ DQ1 DQ0 DQ3 DQ4 DQ7 DQ6 DQ5 VCCQ VSSQ A B C D E TOP VIEW (Ball Down) 24 Balls TFBGA, 5x5-1 Ball Footprint, Top View The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 4 - W959D8NFYA 4. BALL DESCRIPTIONS Signal Name Type Description Input Chip Select: Bus transactions are initiated with a High to Low transition. Bus transactions are terminated with a Low to High transition. The master device has a separate CS# for each slave. CK, CK# Input Differential Clock: Command, address, and data information is output with respect to the crossing of the CK and CK# signals. Single Ended Clock: CK# is not used, only a single ended CK is used. The clock is not required to be free-running. DQ[7:0] Input / Output Data Input / Output: Command, Address, and Data information is transferred on these signals during Read and Write transactions. Input / Output Read Write Data Strobe: During the Command/Address portion of all bus transactions RWDS is a slave output and indicates whether additional initial latency is required. Slave output during read data transfer, data is edge aligned with RWDS. Slave input during data transfer in write transactions to function as a data mask. RWDS High indicates additional latency, Low indicates no additional latency. CS# RWDS RESET# Input, Internal Pull-up Hardware Reset: When Low the slave device will self-initialize and return to the Standby state. RWDS and DQ[7:0] are placed into the High-Z state when RESET# is Low. The slave RESET# input includes a weak pull-up, if RESET# is left unconnected it will be pulled up to the High state. VCC Power Supply VCC Power Supply: For supplying input buffer of CK/CK#, CS#, RESET#, DQ[7:0] and RWDS, internal circuitry and memory array. VCCQ Power Supply VCCQ Power Supply: For supplying output buffer of DQ[7:0] and RWDS. VSS Power Supply VSS Ground: Ground of VCC. VSSQ Power Supply VSSQ Ground: Ground of VCCQ. RFU No Connect Reserved for Future Use: May or may not be connected internally, the signal/ball location should be left unconnected and unused by PCB routing channel for future compatibility. The signal/ball may be used by a signal in the future. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 5 - W959D8NFYA X Decoders 5. BLOCK DIAGRAM 5.1 Function Block Diagram (Single Die) CS# CK/CK# RWDS DQ[7:0] I/O Control Logic Memory Y Decoders Data Latch RESET# Data Path The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 6 - W959D8NFYA 5.2 Package Block Diagram (Dual Die Package) CS# CS# CK CK CK# RWDS RESET# CK# VCC VCCQ 256M bits HyperRAM Die 0 VSSQ RWDS DQ[7:0] RESET# CS# RWDS RESET# VCCQ VSS VSSQ DQ[7:0] VCC CK CK# VSS VCC VCCQ 256M bits HyperRAM Die 1 VSS VSSQ DQ[7:0] The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 7 - W959D8NFYA 6. FUNCTIONAL DESCRIPTION 6.1 HyperBus HyperBus is a low signal count, Double Data Rate (DDR) interface, that achieves high speed read and write throughput. The DDR protocol transfers two data bytes per clock cycle on the DQ input/output signals. A read or write transaction on HyperBus consists of a series of 16-bit wide, one clock cycle data transfers at the internal HyperRAM array with two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals. All inputs and outputs are LV-CMOS compatible. Command, address, and data information is transferred over the eight HyperBus DQ[7:0] signals. The clock (CK#, CK) is used for information capture by a HyperBus slave device when receiving command, address, or data on the DQ signals. Command or Address values are center aligned with clock transitions. Every transaction begins with the assertion of CS# and Command-Address (CA) signals, followed by the start of clock transitions to transfer six CA bytes, followed by initial access latency and either read or write data transfers, until CS# is de-asserted. Read and write transactions require two clock cycles to define the target row address and burst type, then an initial access latency of tACC. During the CA part of a transaction, the memory will indicate whether an additional latency for a required refresh time (tRFH) is added to the initial latency; by driving the RWDS signal to the High state. During the CA period the third clock cycle will specify the target word address within the target row. During a read (or write) transaction, after the initial data value has been output (or input), additional data can be read from (or written to) the row on subsequent clock cycles in either a wrapped or linear sequence. When configured in linear burst mode, the device will automatically fetch the next sequential row from the memory array to support a continuous linear burst. Simultaneously accessing the next row in the array while the read or write data transfer is in progress, allows for a linear sequential burst operation that can provide a sustained data rate of 500 MB/s (1 byte (8 bit data bus) * 2 (data clock edges) * 250 MHz = 500 MB/s). Once linear burst reaches the last address of 256Mb of the accessed die, then the addressing will go back to minimum address of the die. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 8 - W959D8NFYA The Read/Write Data Strobe (RWDS) is a bidirectional signal that indicates: ⚫ When data will start to transfer from a HyperRAM device to the master device in read transactions (initial read latency) ⚫ When data is being transferred from a HyperRAM device to the master device during read transactions (as a source synchronous read data strobe) ⚫ When data may start to transfer from the master device to a HyperRAM device in write transactions (initial write latency) ⚫ Data masking during write data transfers During the CA transfer portion of a read or write transaction, RWDS acts as an output from a HyperRAM device to indicate whether additional initial access latency is needed in the transaction. During read data transfers, RWDS is read data strobe with data values edge aligned with the transitions of RWDS. CS# tRWR = Read Write Recovery Additional Latency tACC = Access CK#,CK Latency Count 1 RWDS Latency Count 2 High = 2x Latency Count RWDS and Data are edge aligned DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 Command-Address Dn A Dn B Dn+1 A Dn+1 B Memory drives DQ[7:0] and RWDS Figure 1 - Read Transaction, Additional Latency Count During write data transfers, RWDS indicates whether each data byte transfer is masked with RWDS High (invalid and prevented from changing the byte location in a memory) or not masked with RWDS Low (valid and written to a memory). Data masking may be used by the host to byte align write data within a memory or to enable merging of multiple nonword aligned writes in a single burst write. During write transactions, data is center aligned with clock transitions. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 9 - W959D8NFYA Read and write transactions are burst oriented, transferring the next sequential word during each clock cycle. Each individual read or write transaction can use either a wrapped or linear burst sequence. 16 word group alignment boundaries Linear Burst 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h Initial address = 4h Wrapped Burst 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh Figure 2 - Linear Versus Wrapped Burst Sequence During wrapped transactions, accesses start at a selected location and continue to the end of a configured word group aligned boundary, then wrap to the beginning location in the group, then continue back to the starting location. Wrapped bursts are generally used for critical word first cache line fill read transactions. During linear transactions, accesses start at a selected location and continue in a sequential manner until the transaction is terminated when CS# returns High. Linear transactions are generally used for large contiguous data transfers such as graphic images. Since each transaction command selects the type of burst sequence for that transaction, wrapped and linear bursts transactions can be dynamically intermixed as needed. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 10 - W959D8NFYA 7. HyperBus TRANSACTION DETAILS 7.1 Command/Address Bit Assignments All HyperRAM bus transactions can be classified as either read or write. A bus transaction is started with CS# going Low with clock in idle state (CK=Low and CK#=High). The first three clock cycles transfer three words of Command/Address (CA0, CA1, CA2) information to define the transaction characteristics. The Command/Address words are presented with DDR timing, using the first six clock edges. The following characteristics are defined by the Command/Address information: ◼ Read or Write transaction ◼ Address Space: memory array space or register space – Register space is used to access Device Identification (ID) registers and Configuration Registers (CR) that identify the device characteristics and determine the slave specific behavior of read and write transfers on the HyperBus. ◼ Whether a transaction will use a linear or wrapped burst sequence ◼ The target row (and half-page) address (upper order address) ◼ The target column (word within half-page) address (lower order address) CS# CK,CK# DQ[7:0] CA0[47:40] CA0[39:32] CA1[31:24] CA1[23:16] CA2[15:8] CA2[7:0] Figure 3 - Command-Address (CA) Sequence Notes: 1. Figure shows the initial three clock cycles of all transactions on the HyperBus. 2. CK# of differential clock is shown as dashed line waveform. 3. CA information is “center aligned” with the clock during both Read and Write transactions. 4. Data bits in each byte are always in high to low order with bit 7 on DQ7 and bit 0 on DQ0. Table 1 - CA Bit Assignment to DQ Signals Signal CA0[47:40] CA0[39:32] CA1[31:24] CA1[23:16] CA2[15:8] CA2[7:0] DQ[7] CA[47] CA[39] CA[31] CA[23] CA[15] CA[7] DQ[6] CA[46] CA[38] CA[30] CA[22] CA[14] CA[6] DQ[5] CA[45] CA[37] CA[29] CA[21] CA[13] CA[5] DQ[4] CA[44] CA[36] CA[28] CA[20] CA[12] CA[4] DQ[3] CA[43] CA[35] CA[27] CA[19] CA[11] CA[3] DQ[2] CA[42] CA[34] CA[26] CA[18] CA[10] CA[2] DQ[1] CA[41] CA[33] CA[25] CA[17] CA[9] CA[1] DQ[0] CA[40] CA[32] CA[24] CA[16] CA[8] CA[0] The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 11 - W959D8NFYA Table 2 - Command/Address Bit Assignments CA Bit# Bit Name 47 R/W# 46 45 44-16 Address Space (AS) Burst Type Bit Function Identifies the transaction as a read or write. R/W#=1 indicates a Read transaction R/W#=0 indicates a Write transaction Indicates whether the read or write transaction accesses the memory or register space. AS=0 indicates memory space AS=1 indicates the register space The register space is used to access device ID and Configuration registers. Indicates whether the burst will be linear or wrapped. Burst Type=0 indicates wrapped burst Burst Type=1 indicates linear burst Row & Upper Column component of the target address: System word address bits A31-A3 Row & Upper Column Address Any upper Row address bits not used by a particular device density should be set to 0 by the host controller master interface. The size of Rows and therefore the address bit boundary between Row and Column address is slave device dependent. 15-3 Reserved 2-0 Lower Column Address Reserved for future column address expansion. Reserved bits are don’t care in current HyperBus devices but should be set to 0 by the host controller master interface for future compatibility. Lower Column component of the target address: System word address bits A2-A0 selecting the starting word within a half-page. Notes: 1. The Column address selects the burst transaction starting word location within a Row. The Column address is split into an upper and lower portion. The upper portion selects an 8-word (16-byte) Half-page and the lower portion selects the word within a Half-page where a read or write transaction burst starts. 2. The initial read access time starts when the Row and Upper Column (Half-page) address bits are captured by a slave interface. Continuous linear read burst is enabled by memory devices internally interleaving access to 16 byte half-pages.. 3. HyperBus protocol address space limit, assuming: 29 Row &Upper Column address bits 3 Lower Column address bits Each address selects a word wide (16 bit = 2 byte) data value 29 + 3 = 32 address bits = 4G addresses supporting 8Gbyte (64Gbit) maximum address space The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 12 - W959D8NFYA CS# CK,CK# RWDS DQ[7:0] Dn A Dn B Dn+1 AA Dn+1 Dn+1 B Dn+2 A Figure 4 - Data Placement during a Read Transaction Notes: 1. Figure shows a portion of a Read transaction on the HyperBus. CK# of differential clock is shown as dashed line waveform. 2. Data is “edge aligned” with the RWDS serving as a read data strobe during read transactions. 3. Data is always transferred in full word increments (word granularity transfers). 4. Word address increments in each clock cycle. Byte A is between RWDS rising and falling edges and is followed by byte B between RWDS falling and rising edges, of each word. 5. Data bits in each byte are always in high to low order with bit 7 on DQ7 and bit 0 on DQ0. CS# CK,CK# RWDS DQ[7:0] Dn A Dn B Dn+1 AA Dn+1 Dn+1 B Dn+2 A Figure 5 - Data Placement during a Write Transaction Notes: 1. Figure shows a portion of a Write transaction on the HyperBus. 2. Data is “center aligned” with the clock during a Write transaction. 3. RWDS functions as a data mask during write data transfers with initial latency. Masking of the first and last byte is shown to illustrate an unaligned 3 byte write of data. 4. RWDS is not driven by the master during write data transfers with zero initial latency. Full data words are always written in this case. RWDS may be driven Low or left High-Z by the slave in this case. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 13 - W959D8NFYA 7.2 Read Transactions The HyperBus master begins a transaction by driving CS# Low while clock is idle. The clock then begins toggling while CA words are transferred. In CA0, CA[47] = 1 indicates that a Read transaction is to be performed. CA[46] = 0 indicates the memory space is being read or CA[46] = 1 indicates the register space is being read. CA[45] indicates the burst type (wrapped or linear). Read transactions can begin the internal array access as soon as the row and upper column address has been presented in CA0 and CA1 (CA[47:16]). CA2 (CA(15:0]) identifies the target Word address within the chosen row. The HyperBus master then continues clocking for a number of cycles defined by the latency count setting in Configuration Register 0. The initial latency count required for a particular clock frequency is based on RWDS. If RWDS is High during the CA cycles, an additional latency count is inserted. Once these latency clocks have been completed the memory starts to simultaneously transition the Read-Write Data Strobe (RWDS) and output the target data. New data is output edge aligned with every transition of RWDS. Data will continue to be output as long as the host continues to transition the clock while CS# is Low. However, the HyperRAM device may stop RWDS transitions with RWDS Low, between the deliveries of words, in order to insert latency between words when crossing memory array boundaries. Wrapped bursts will continue to wrap within the burst length and linear burst will output data in a sequential manner across row boundaries. When a linear burst read reaches the last address in the array, continuing the burst beyond the last address will provide data from the beginning of the address range. Read transfers can be ended at any time by bringing CS# High when the clock is idle. The clock is not required to be free-running. The clock may remain idle while CS# is High. CS# tRWR = Read Write Recovery Additional Latency tACC = Access CK#,CK RWDS High = 2x Latency Count Latency Count 1 DQ[7:0] 47:40 39:32 31:24 23:16 15:8 Latency Count 2 7:0 Command-Address RWDS and Data are edge aligned Dn A Dn B Dn+1 A Dn+1 B Memory drives DQ[7:0] and RWDS Figure 6 - Read Transaction with Additional Initial Latency Notes: 1. Transactions are initiated with CS# falling while CK=Low and CK#=High. 2. CS# must return High before a new transaction is initiated. 3. CK# is the complement of the CK signal.CK# of a differential clock is shown as a dashed line waveform. 4. Read access array starts once CA[23:16] is captured. 5. The read latency is defined by the initial latency value in a configuration register. 6. In this read transaction example the initial latency count was set to four clocks. 7. In this read transaction a RWDS High indication during CA delays output of target data by an additional four clocks. 8. The memory device drives RWDS during read transactions. 9. For register read, the output data Dn A is RG[15:8], Dn B is RG[7:0], Dn+1 A is RG[15:8], Dn+1 B is RG[7:0]. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 14 - W959D8NFYA 7.3 Write Transactions (Memory Array Write) The HyperBus master begins a transaction by driving CS# Low while clock is idle. Then the clock begins toggling while CA words are transferred. In CA0, CA[47] = 0 indicates that a Write transaction is to be performed. CA[46] = 0 indicates the memory space is being written. CA[45] indicates the burst type (wrapped or linear). Write transactions can begin the internal array access as soon as the row and upper column address has been presented in CA0 and CA1 (CA[47:16]). CA2 (CA(15:0]) identifies the target word address within the chosen row. The HyperBus master then continues clocking for a number of cycles defined by the latency count setting in configuration register 0. The initial latency count required for a particular clock frequency is based on RWDS. If RWDS is High during the CA cycles, an additional latency count is inserted. Once these latency clocks have been completed the HyperBus master starts to output the target data. Write data is center aligned with the clock edges. The first byte of data in each word is captured by the memory on the rising edge of CK and the second byte is captured on the falling edge of CK. During the CA clock cycles, RWDS is driven by the memory. During the write data transfers, RWDS is driven by the host master interface as a data mask. When data is being written and RWDS is High the byte will be masked and the array will not be altered. When data is being written and RWDS is Low the data will be placed into the array. Because the master is driving RWDS during write data transfers, neither the master nor the HyperRAM device is able to indicate a need for latency within the data transfer portion of a write transaction. The acceptable write data burst length setting is also shown in configuration register 0. Data will continue to be transferred as long as the HyperBus master continues to transition the clock while CS# is Low. Legacy format wrapped bursts will continue to wrap within the burst length. Hybrid wrap will wrap once then switch to linear burst starting at the next wrap boundary. Linear burst accepts data in a sequential manner across page boundaries. Write transfers can be ended at any time by bringing CS# High when the clock is idle. When a linear burst write reaches the last address in the memory array space, continuing the burst will write to the beginning of the address range. The clock is not required to be free-running. The clock may remain idle while CS# is High. CS# tRWR = Read Write Recovery Additional Latency tACC = Initial Access CK#,CK Latency Count 1 RWDS DQ[7:0] Latency Count 2 CK and Data are center aligned High = 2x Latency Count 47:40 39:32 31:24 23:16 15:8 7:0 Command-Address Host drives DQ[7:0] and Memory drives RWDS Dn A Dn B Dn+1 A Dn+1 Dn+1 AB Host drives DQ[7:0] and RWDS Figure 7 - Write Transaction with Additional Initial Latency Notes: 1. Transactions must be initiated with CK=Low and CK#=High. 2. CS# must return High before a new transaction is initiated. 3. During CA, RWDS is driven by the memory and indicates whether additional latency cycles are required. 4. In this example, RWDS indicates that additional initial latency cycles are required. 5. At the end of CA cycles the memory stops driving RWDS to allow the host HyperBus master to begin driving RWDS. The master must drive RWDS to a valid Low before the end of the initial latency to provide a data mask preamble period to the slave. 6. During data transfer, RWDS is driven by the host to indicate which bytes of data should be either masked or loaded into the array. 7. The figure shows RWDS masking byte Dn A and byte Dn+1 B to perform an unaligned word write to bytes Dn B and Dn+1 A. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 15 - W959D8NFYA 7.4 Write Transactions without Initial Latency (Register Write) A Write transaction starts with the first three clock cycles providing the Command/Address information indicating the transaction characteristics. CA0 may indicate that a Write transaction is to be performed and also indicates the address space and burst type (wrapped or linear). Writes without initial latency are used for register space writes. HyperRAM device write transactions with zero latency mean that the CA cycles are followed by write data transfers. Writes with zero initial latency, do not have a turnaround period for RWDS. The HyperRAM device will always drive RWDS during the CA period to indicate whether extended latency is required for a transaction that has initial latency. However, the RWDS is driven before the HyperRAM device has received the first byte of CA i.e. before the HyperRAM device knows whether the transaction is a read or write to register space. In the case of a write with zero latency, the RWDS state during the CA period does not affect the initial latency of zero. Since master write data immediately follows the CA period in this case, the HyperRAM device may continue to drive RWDS Low or may take RWDS to High-Z during write data transfer. The master must not drive RWDS during Writes with zero latency. Writes with zero latency do not use RWDS as a data mask function. All bytes of write data are written (full word writes). The first byte of data in each word is presented on the rising edge of CK and the second byte is presented on the falling edge of CK. Write data is center aligned with the clock inputs. Write transfers can be ended at any time by bringing CS# High when clock is idle. The clock is not required to be free-running. CS# CK,CK# RWDS DQ[7:0] CA [47:40] CA [39:32] CA [31:24] CA [23:16] CA [15:8] CA [7:0] RG [15:8] RG [7:0] Command-Address Figure 8 - Write Operation without Initial Latency (Register Write) The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 16 - W959D8NFYA 8. MEMORY SPACE 8.1 HyperBus Memory Space addressing Table 3 - Memory Space Address Map (word based – 16-bits) Unit Type Count System Word Address Bits CA Bits Rows within 512 Mb device 65536 (Rows) A24~A9 37~22 Row 1 (row) A8~A3 21~16 Half-Page 8 (word) A2~A0 2~0 Notes 512 (word addresses) 1K bytes 8 words (16 bytes) Table 4 - Memory Space Address Map (word based – 16-bits) 512Mb Row Address Column Address Half-Page (HP) Address Word of HP Address System Word Address Bits A24~A9 CA Bits 37~22 System Word Address Bits A8~A0 CA Bits 21~16; 2~0 System Word Address Bits A8~A3 CA Bits 21~16 System Word Address Bits A2~A0 CA Bits 2~0 Notes: 1. Each row has 64 Half-pages. Each Half-page has 8 words. Each column has 512 words (1K bytes). 2. Half-Page address is also named as upper column address. Word of HP address is also named as lower column address. 8.1.1 Density and Row Boundaries The DRAM array size (density) of the device can be determined from the total number of system address bits used for the row and column addresses as indicated by the Row Address Bit Count and Column Address Bit Count fields in the ID0 register. For example: a 256-Mbit HyperRAM device has 9 column address bits and 15 row address bits for a total of 24 word address bits = 224 = 16M words = 32M bytes. The 9 column address bits indicate that each row holds 2 9 = 512 words = 1K bytes. The row address bit count indicates there are 32768 rows to be refreshed within each array refresh interval. The row count is used in calculating the refresh interval. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 17 - W959D8NFYA 9. REGISTER SPACE 9.1 HyperBus Register Addressing Table 5 - Register Space Address Map (for 2 Die DDP 512Mb) Register System Address CA Bits 512 Mb Identification Register 0 - Die 0 512 Mb Identification Register 0 - Die 1 512 Mb Identification Register 1 - Die 0 512 Mb Identification Register 1 - Die 1 512 Mb Configuration Register 0 - Die 0 512 Mb Configuration Register 0 - Die 1 512 Mb Configuration Register 1 - Die 0 512 Mb Configuration Register 1 - Die 1 512 Mb Configuration Register 0 - Die 0/1 512 Mb Configuration Register 1 - Die 0/1 — — — 31~27 26~24 23~22 21~19 18~11 10~3 — 2~0 47 46 45 44~40 39~37 36~35 34~32 31~24 23~16 15~8 7~0 Read 000b 00b 000b 00h 00h 00h 00h Read 001b 00b 000b 00h 00h 00h 00h Read 000b 00b 000b 00h 00h 00h 01h Read 001b 00b 000b 00h 00h 00h 01h Read 000b 00b 000b 01h 00h 00h 00h Read 001b 00b 000b 01h 00h 00h 00h Read 000b 00b 000b 01h 00h 00h 01h Read 001b 00b 000b 01h 00h 00h 01h Write 000b 00b 000b 01h 00h 00h 00h Write 000b 00b 000b 01h 00h 00h 01h Notes: 1. When CA[46] is 1, a read or write transaction accesses the Register Space. 2. CA[45] may be either 0 or 1 for either wrapped or linear read. CA[45] must be 1 as only linear single word register writes are supported. 3. Register write is written in both die at the same time. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 18 - W959D8NFYA 9.2 Register Space Access Register default values are loaded upon power-up or hardware reset. The registers can be altered at any time while the device is in the standby state. Loading a register is accomplished with write transaction without initial latency using a single 16-bit word write transaction. Each register is written with a separate single word write transaction. Register write transactions have zero latency, the single word of data immediately follows the CA. RWDS is not driven by the host during the write because RWDS is always driven by the memory during the CA cycles to indicate whether a memory array refresh is in progress. Because a register space write goes directly to a register, rather than the memory array, there is no initial write latency, related to an array refresh that may be in progress. In a register write, RWDS is also not used as a data mask because both bytes of a register are always written and never masked. Register write is written in both Die at the same time for DDP structure. Reserved register fields must be written with their default value. Writing reserved fields with other than default values may produce undefined results. Note: The host must not drive RWDS during a write to register space. Note: The RWDS signal is driven by the memory during the CA period based on whether the memory array is being refreshed. This refresh indication does not affect the writing of register data. Note: The RWDS signal returns to high impedance after the CA period. Register data is never masked. Both data bytes of the register data are loaded into the selected register. Reading of a register is accomplished with read transaction with double initial latency using a single 16 bit read transaction. If more than one word is read, the same register value is repeated in each word read. The contents of the register is returned in the same manner as reading array data, with two latency counts, based on the state of RWDS during the CA period. The latency count is defined in the Configuration Register 0 Read Latency field (CR0[7:4]). The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 19 - W959D8NFYA 9.3 Device Identification Registers There are two read only, non-volatile, word registers, that provide information on the device selected when CS# is low. The device information fields identify: ◼ Manufacture ◼ Type ◼ Density – Row address bit count – Column address bit count Table 6 - ID Register 0 Bit Assignments Bits Function Settings (Binary) 00b - Die 0 01b - Die 1 10b - Reserved 11b - Reserved [15:14] DDP Die Address [13] Reserved [12:8] Row Address Bit Count 01111b - Sixteen Row address bits [7:4] Column Address Bit Count 1000b - Nine column address bits [3:0] Manufacturer 0b - default 0110b - Winbond Table 7 - ID Register 1 Bit Assignments 9.4 Bits Function Settings (Binary) [15:4] Reserved 0000_0000_0000b (default) [3:0] Device Type 0001b - HyperRAM 2.0 0000b, 0010b to 1111b - Reserved Configuration Register 0 Configuration Register 0 (CR0) is used to define the power state and access protocol operating conditions for the HyperRAM device. Configurable characteristics include: ◼ Wrapped Burst Length (16, 32, 64, or 128 bytes aligned and length data group) ◼ Wrapped Burst Type – Legacy wrapped burst (sequential access with wrap around within a selected length and aligned group) – Hybrid burst (Legacy wrapped burst once then linear burst at start of the next sequential group) ◼ Initial Latency ◼ Fixed Latency – The memory array read or writes transaction use fixed latency will always indicate a refresh latency and delay the read data transfer accordingly. ◼ Output Drive Strength ◼ Deep Power Down Mode The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 20 - W959D8NFYA Table 8 - Configuration Register 0 Bit Assignments CR0 Bit Function [15] Deep Power Down Enable [14:12] Drive Strength [11:8] Reserved [7:4] [3] Fixed Latency Enable [2] Hybrid Burst Enable [1:0] 9.4.1 Initial Latency Burst Length Settings (Binary) 1b - Normal operation (default) 0b - Deep Power Down mode Note: HyperRAM will automatically set the value of CR0[15] to “1” after exit DPD. 000b - 34 ohms (default) 001b - 115 ohms 010b - 67 ohms 011b - 46 ohms 100b - 34 ohms 101b - 27 ohms 110b - 22 ohms 111b - 19 ohms 1b - Reserved (default) Reserved for Future Use. When writing this register, these bits should be set to 1 for future compatibility. 0000b - 5 Clock Latency @ 133MHz Max Frequency 0001b - 6 Clock Latency @ 166MHz Max Frequency 0010b - 7 Clock Latency @ 250MHz Max Frequency (default) ... 1101b - Reserved 1110b - 3 Clock Latency @ 85MHz Max Frequency 1111b - 4 Clock Latency @ 104MHz Max Frequency 1b - Fixed 2 times Initial Latency (default) Note: CR0[3] of each die of this DDP package must be programmed as “1” (Fixed Latency mode). 0b: Wrapped burst sequences to follow hybrid burst sequencing 1b: Wrapped burst sequences in legacy wrapped burst manner (default) 00b - 128 bytes 01b - 64 bytes 10b - 16 bytes 11b - 32 bytes (default) Wrapped Burst A wrapped burst transaction accesses memory within a group of words aligned on a word boundary matching the length of the configured group. Wrapped access groups can be configured as 16, 32, 64, or 128 bytes alignment and length. During wrapped transactions, access starts at the CA selected location within the group, continues to the end of the configured word group aligned boundary, then wraps around to the beginning location in the group, then continues back to the starting location. Wrapped bursts are generally used for critical word first instruction or data cache line fill read accesses. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 21 - W959D8NFYA 9.4.2 Hybrid Burst The beginning of a hybrid burst will wrap within the target address wrapped burst group length before continuing to the next half-page of data beyond the end of the wrap group. Continued access is in linear burst order until the transfer is ended by returning CS# High. This hybrid of a wrapped burst followed by a linear burst starting at the beginning of the next burst group, allows multiple sequential address cache lines to be filled in a single access. The first cache line is filled starting at the critical word. Then the next sequential line in memory can be read in to the cache while the first line is being processed. Table 9 - CR0[2] Control of Wrapped Burst Sequence Bit Default Value 2 1 Name Hybrid Burst Enable CR0[2]= 0b: Wrapped burst sequences to follow hybrid burst sequencing CR0[2]= 1b: Wrapped burst sequences in legacy wrapped burst manner Table 10 - Example Wrapped Burst Sequences (HyperBus Addressing) Burst Type Wrap Boundary Start Address Address Sequence (Hex) (Words) (bytes) (Hex) Hybrid 128 128 Wrap once then Linear XXXXXX03 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 00, 01, 02 (Wrap complete, now linear beyond the end of the initial 128 byte wrap group) 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4A, 4B, 4C, 4D, 4E, 4F, 50, 51, ... Hybrid 64 64 Wrap once then Linear XXXXXX03 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02, (Wrap complete, now linear beyond the end of the initial 64 byte wrap group) 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F, 30, 31, ... Hybrid 64 64 Wrap once then Linear XXXXXX2E 2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, (Wrap complete, now linear beyond the end of the initial 64 byte wrap group) 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4A, 4B, 4C, 4D, 4E, 4F, 50, 51, ... Hybrid 16 16 Wrap once then Linear XXXXXX02 02, 03, 04, 05, 06, 07, 00, 01, (Wrap complete, now linear beyond the end of the initial 16 byte wrap group) 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, ... Hybrid 16 16 Wrap once then Linear XXXXXX0C 0C, 0D, 0E, 0F, 08, 09, 0A, 0B, (Wrap complete, now linear beyond the end of the initial 16 byte wrap group) 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, ... Hybrid 32 32 Wrap once then Linear XXXXXX0A Wrap 64 64 XXXXXX03 Wrap 64 64 XXXXXX2E 2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, ... Wrap 16 16 XXXXXX02 02, 03, 04, 05, 06, 07, 00, 01, ... Wrap 16 16 XXXXXX0C 0C, 0D, 0E, 0F, 08, 09, 0A, 0B, ... Wrap 32 32 XXXXXX0A 0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, ... Linear Linear Burst XXXXXX03 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, ... 0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09 (Wrap complete, now linear beyond the end of the initial 32 byte wrap group) 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, ... 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02, ... Note: Burst across die boundary is not supported in multi-die stack. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 22 - W959D8NFYA 9.4.3 Initial Latency Memory Space read and writes transactions or Register Space read transactions require some initial latency to open the row selected by the CA. This initial latency is tACC. The number of latency clocks needed to satisfy tACC depends on the HyperBus frequency and can vary from 3 to 7 clocks. The value in CR0[7:4] selects the number of clocks for initial latency. The default value is 7 clocks, allowing for operation up to a maximum frequency of 250MHz prior to the host system setting a lower initial latency value that may be more optimal for the system. In the event a distributed refresh is required at the time a Memory Space read or write transaction or Register Space read transaction begins, the RWDS signal goes High during the CA to indicate that an additional initial latency is being inserted to allow a refresh operation to complete before opening the selected row. Register Space write transactions always have zero initial latency. RWDS may be High or Low during the CA period. The level of RWDS during the CA period does not affect the placement of register data immediately after the CA, as there is no initial latency needed to capture the register data. A refresh operation may be performed in the memory array in parallel with the capture of register data. 9.4.4 Fixed Latency A configuration register option bit CR0[3] is provided to make all Memory Space read and write transactions or Register Space read transactions require the same initial latency by always driving RWDS High during the CA to indicate that two initial latency periods are required. This fixed initial latency is independent of any need for a distributed refresh, it simply provides a fixed (deterministic) initial latency for all of these transaction types. The fixed latency option may simplify the design of some HyperBus memory controllers or ensure deterministic transaction performance. Fixed latency is the default POR or reset configuration. The system must not clear this configuration bit to “0b”. 9.4.5 Drive Strength DQ and RWDS signal line loading, length, and impedance vary depending on each system design. Configuration register bits CR0[14:12] provide a means to adjust the DQ[7:0] and RWDS signal output impedance to customize the DQ and RWDS signal impedance to the system conditions to minimize high speed signal behaviors such as overshoot, undershoot, and ringing. The default POR or reset configuration value is 000b to select the mid-point of the available output impedance options. The impedance values shown are typical for both pull-up and pull-down drivers at typical silicon process conditions, nominal operating voltage (1.8 V) and 50°C. The impedance values may vary from the typical values depending on the Process, Voltage, and Temperature (PVT) conditions. Impedance will increase with slower process, lower voltage, or higher temperature. Impedance will decrease with faster process, higher voltage, or lower temperature. Each system design should evaluate the data signal integrity across the operating voltage and temperature ranges to select the best drive strength settings for the operating conditions. 9.4.6 Deep Power Down When the HyperRAM device is not needed for system operation, it may be placed in a very low power consuming state called Deep Power Down (DPD), by writing 0 to CR0[15]. When CR0[15] is cleared to 0, the device enters the DPD state within tDPDIN time and all refresh operations stop. The data in RAM is lost, (becomes invalid without refresh) during DPD state. Exiting DPD requires driving CS# Low then High, POR, or a reset. Only CS# and RESET# signals are monitored during DPD mode. All register content might lost in Deep Power Down State. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 23 - W959D8NFYA 9.5 Configuration Register 1 Configuration Register 1 (CR1) is used to define the refresh array size, refresh rate and Hybrid Sleep for the HyperRAM device. Configurable characteristics include: ◼ Partial Array Refresh ◼ Hybrid Sleep State ◼ Refresh Rate Table 11 - Configuration Register 1 Bit Assignments CR1 Bit Function Settings (Binary) [15-8] Reserved FFh - Reserved (default) Reserved for Future Use. When writing this register, these bits should keep FFh for future compatibility. [7] Reserved 1b - Reserved (default) When writing this register, this bit should keep 1b. [6] Master Clock Type [5] Hybrid Sleep [4:2] Partial Array Refresh [1:0]*1 Distributed Refresh Interval 1b - Single Ended - CK (default) 0b - Differential - CK#, CK 1b - Writing 1 to CR1[5] causes the device to enter Hybrid Sleep (HS) State 0b - Normal operation (default) 000b - Full Array (default) 001b - Bottom 1/2 Array 010b - Bottom 1/4 Array 011b - Bottom 1/8 Array 100b - Reserved 101b - Top 1/2 Array 110b - Top 1/4 Array 111b - Top 1/8 Array 10b - Reserved 11b - Reserved 00b - Reserved 01b - 4μs (tCSM) Note: 1. CR1[1:0] is read only. 9.5.1 Master Clock Type Two clock types, namely single ended and differential, are supported by HyperRAM. CR1[6] selects which type to use. 9.5.2 Partial Array Refresh The partial array refresh configuration restricts the refresh operation in HyperRAM to a portion of the memory array specified by CR1[4:2]. This reduces the standby current. The default configuration refreshes the whole array. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 24 - W959D8NFYA 9.5.3 Hybrid Sleep When the HyperRAM is not needed for system operation, it may be placed in Hybrid Sleep state if data in the device needs to be retained. Enter Hybrid Sleep state by writing 1 to CR1[5]. Bringing CS# Low will cause the device to exit HS state and set CR1[5] to 0. Also, POR, or a hardware reset will cause the device to exit Hybrid Sleep state. Note that a POR or a hardware reset disables refresh where the memory core data can potentially get lost. 9.5.4 Distributed Refresh Interval The HyperRAM device is built with volatile memory array which requires periodic refresh of all bits in the array. The refresh operation can be done by an internal self-refresh logic that will evenly refresh the memory array automatically. The automatic refresh operation can only be done when the memory array is not being actively read or written by the host system. The refresh logic waits for the end of any active read or write before doing a refresh, if a refresh is needed at that time. If a new read or write begins before the refresh is completed, the memory will drive RWDS high during the CA period to indicate that an additional initial latency time is required at the start of the new access in order to allow the refresh operation to complete before starting the new access. The evenly distributed refresh operations requires a maximum refresh interval between two adjacent refresh operations. The maximum distributed refresh interval will varies with temperature as shown in Table 12 - Distributed Refresh Interval per Temperature. Table 12 - Distributed Refresh Interval per Temperature Device Temperature (TCASE °C) Maximum Distributed Refresh Interval (µS) CR1[1:0] TCASE < 85 4 01b The distributed refresh operation requires that the host does not do burst transactions longer than the distributed refresh interval to prevent the memory from unable doing the distributed refreshes operation when it is needed. This sets an upper limit on the length of read and write transactions so that the automatic distributed refresh operation can be done between transactions. This limit is called the CS# low maximum time (tCSM) and the tCSM will be equal to the maximum distributed refresh interval. The host system is required to respect the tCSM value by ending each transaction before violating tCSM. This can be done by host memory controller logic splitting long transactions when reaching the tCSM limit, or by host system hardware or software not performing a single read or write transaction that would be longer than tCSM. As noted in Table 12 of distributed refresh interval, the maximum refresh interval is longer at lower temperatures such that tCSM could be increased to allow longer transactions. The host system can either use the CR1[1:0] value from the table for the maximum operating temperature or, may determine the current operating temperature from a temperature sensor in the system in order to set a longer distributed refresh interval. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 25 - W959D8NFYA 9.6 Dual-Die-Package (DDP) Application 9.6.1 Die Stack Addressing Table 13 - Die Stack Addressing 9.6.2 Die # HyperBus System Address Die 0 00FFFFFFh ~ 00000000h Die 1 01FFFFFFh ~ 01000000h Burst Operations - Die Boundary Crossing Burst operation can be performed within one die. However, Burst reads and writes are not allowed crossing die boundaries. 9.6.3 Die number assignment Each die in a DDP is allocated with different die number (Die 0 and Die 1). 9.6.4 Latency mode For this DDP package Variable Latency mode is not allowed. Every operation must be under fixed latency mode and the CR0 [3] must be programmed as “1”. The CR0 [3] is defined as below. CR0 Bit [3] Function Fixed Latency Enable Settings (Binary) 1b - Fixed 2 times Initial Latency (default) Note: CR0[3] of each die of this DDP package must be programmed as “1” (Fixed Latency mode). In fixed latency mode, when CS# asserted LOW, 1. The RWDS signal of each die of DDP will always drive to HIGH during CA phase; 2. The RWDS signal of the non-selected die of DDP will always drive to Hi-Z after CA phase; 3. The RWDS signal of the selected die of DDP will drive to L after CA phase. 9.6.5 IO pad capacitance For this DDP package all IO pad of each stacked die share same IO pin of package. It means that the IO capacitance of each IO pin of package will be 2 times than an IO pad of each stacked die. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 26 - W959D8NFYA 9.6.6 Current consumption For this DDP package the current consumption of standby will be 2 times than the consumption of each stacked die. 9.6.7 Partial Refresh For this DDP package the area under partial refresh will be allocated into partial area of each stacked die. CR1 Bit [4:2] Function Partial Array Refresh Settings (Binary) Active Area of Die 1 Active Area of Die 0 000 b - Full Array of 512Mb space (default) Full Array of Die 1 Full Array of Die 0 001 b - Bottom 1/2 Array of 512Mb space None Full Array of Die 0 010 b - Bottom 1/4 Array of 512Mb space None Bottom 1/2 Array of Die 0 011 b - Bottom 1/8 Array of 512Mb space None Bottom 1/4 Array of Die 0 100 b - Reserved None None 101 b - Top 1/2 Array of 512Mb space Full Array of Die 1 None 110 b - Top 1/4 Array of 512Mb space Top 1/2 Array of Die 1 None 111 b - Top 1/8 Array of 512Mb space Top 1/4 Array of Die 1 None The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 27 - W959D8NFYA 10. INTERFACE STATES 10.1 IO condition of interface states Below Interface States table describes the required value of each signal for each interface state. Table 14 - Interface States Interface State VCC / VCCQ CS# CK, CK# DQ7-DQ0 RWDS RESET# < VLKO X X High-Z High-Z X Power-On (Cold) Reset VCC / VCCQ min X X High-Z High-Z X Hardware (Warm) Reset VCC / VCCQ min X X High-Z High-Z L Interface Standby VCC / VCCQ min H X High-Z High-Z H CA VCC / VCCQ min L T Master Output Valid X H Read Initial Access Latency (data bus turn around period) VCC / VCCQ min L T High-Z L H Write Initial Access Latency (RWDS turn around period) VCC / VCCQ min L T High-Z High-Z H Read data transfer VCC / VCCQ min L T Slave Output Valid Slave Output Valid X or T H Write data transfer with Initial Latency VCC / VCCQ min L T Master Output Valid Master Output Valid X or T H Write data transfer without Initial Latency *1 VCC / VCCQ min L T Master Output Valid Slave Output L or High-Z H Active Clock Stop VCC / VCCQ min L Idle Master or Slave Output Valid or High-Z X H Deep Power Down VCC / VCCQ min H X or T High-Z High-Z H Hybrid Sleep VCC / VCCQ min H X or T High-Z High-Z H Power-Off Legend L = VIL H = VIH X = either VIL, VIH, VOL or VOH L/H = rising edge H/L = falling edge T = Toggling during information transfer Idle = CK is Low and CK# is High. Valid = all bus signals have stable L or H level Note: 1. Writes without initial latency (with zero initial latency), do not have a turnaround period for RWDS. The HyperRAM device will always drive RWDS during the CA period to indicate whether extended latency is required. Since master write data immediately follows the CA period the HyperRAM device may continue to drive RWDS Low or may take RWDS to High-Z. The master must not drive RWDS during Writes with zero latency. Writes with zero latency do not use RWDS as a data mask function. All bytes of write data are written (full word writes). The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 28 - W959D8NFYA 10.2 Power Conservation Modes 10.2.1 Interface Standby Standby is the default, low power, state for the interface while the device is not selected by the host for data transfer (CS#= High). All inputs and outputs other than CS# and RESET# are ignored in this state. 10.2.2 Active Clock Stop The Active Clock Stop state reduces device interface energy consumption to the ICC6 level during the data transfer portion of a read or write operation. The device automatically enables this state when clock remains stable for tACC + 30 nS. While in Active Clock Stop state, read data is latched and always driven onto the data bus. Active Clock Stop state helps reduce current consumption when the host system clock has stopped to pause the data transfer. Even though CS# may be Low throughout these extended data transfer cycles, the memory device host interface will go into the Active Clock Stop current level at tACC + 30 nS. This allows the device to transition into a lower current state if the data transfer is stalled. Active read or write current will resume once the data transfer is restarted with a toggling clock. The Active Clock Stop state must not be used in violation of the tCSM limit. CS# must go High before tCSM is violated. Note that it is recommended to stop the clock when it is in Low state. Read – Clock Stopped CS# CK#,CK Clock Stopped Latency Count (2x) High: 2x Latency Count RWDS RWDS & Data are edge aligned DQ[7:0] 47:40 39:32 31:24 23:16 15:8 DoutA [7:0] 7:0 DoutB [7:0] DoutA+1 [7:0] DoutB+1 [7:0] Read Data Command - Address Figure 9 - Active Clock Stop during Read Transaction (DDR) 10.2.3 Hybrid Sleep In the Hybrid Sleep (HS) state, the current consumption is reduced (IHS). HS state is entered by writing a 1 to CR1[5]. The device reduces power within tHSIN time. The data in Memory Space and Register Space is retained during HS state. Bringing CS# Low will cause the device to exit HS state and set CR1[5] to 0. Also, POR, or a hardware reset will cause the device to exit HS state. Returning to Standby state requires tEXTHS time. Following the exit from HS due to any of these events, the device is in the same state as entering HS. CS# CK#,CK RWDS High: 2x Latency Count tHSIN DQ[7:0] 47:40 39:32 31:24 23:16 Command - Address 15:8 7:0 15:8 7:0 Write Data CR1 Value Enter Hybrid Sleep HS Figure 10 - Enter Hybrid Sleep Transaction The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 29 - W959D8NFYA CS# tCSHS tEXTHS Figure 11 - Exit Hybrid Sleep Transaction 10.2.4 Deep Power Down In the Deep Power down (DPD) state, current consumption is driven to the lowest possible level (IDPD). DPD state is entered by writing a 0 to CR0[15]. The device reduces power within tDPDIN time and all refresh operations stop. The data in Memory Space is lost, (becomes invalid without refresh) during DPD state. Driving CS# Low then High will cause the device to exit DPD state. Also, POR, or a hardware reset will cause the device to exit DPD state. Returning to Standby state requires tEXTDPD time. Returning to Standby state following a POR requires tVCS time, as with any other POR. Following the exit from DPD due to any of these events, the device is in the same state as following POR. CS# CK#,CK High: 2x Latency Count RWDS tDPDIN DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 15:8 Command - Address 7:0 Write Data CR0 Value Enter Deep Power Down tDPDIN DPD Figure 12 - Enter DPD Transaction CS# tCSDPD tEXTDPD Figure 13 - Exit DPD Transaction The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 30 - W959D8NFYA 11. ELECTRICAL SPECIFICATIONS 11.1 Absolute Maximum Ratings Parameter Voltage on VCC,VCCQ supply relative to VSS Voltage to any ball except VCC relative to VSS Soldering temperature and time 10s (solder ball only) Storage temperature (plastic) Min -0.5 -0.5 Max VCC +0.5 VCC +0.5 Unit V V °C °C mA +260 -65 +150 100 Output Short Circuit Current Notes 1 1 1 1 1, 2 Notes: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 11.2 Latch up Characteristics Table 15 - Latch up Specification Description Min Max Unit Input voltage with respect to VSS on all input only connections -1.0 VCC + 1.0 V Input voltage with respect to VSSQ on all I/O connections -1.0 VCCQ + 1.0 V VCCQ Current -100 +100 mA Note: 1. Excludes power supplies VCC/VCCQ. Test conditions: VCC = VCCQ, one connection at a time tested, connections not being tested are at VSS. 11.3 Operating Ranges 11.3.1 DC Characteristics Parameter Description Min Max Unit VCC,VCCQ Power Supply Test Conditions 1.7 2.0 V VIL Input Low Voltage -0.15 x VCC 0.3 x VCC V VIH Input High Voltage 0.7 x VCC 1.15 x VCC V VOL VOH Output Low Voltage Output High Voltage – VCCQ – 0.2 0.2 – V V IOL = 100µA for DQ[7:0] IOH = 100µA for DQ[7:0] Note: 1. All parts list in order information table (section 2) will not guarantee to meet functional and AC specification if the VCC, VCCQ operation condition out of range mentioned in above table. 11.3.2 Operating Temperature Range Parameter Operating Temperature Symbol Range Unit Notes TCASE -40~85 °C 1 Note: 1. All parts list in order information table (section 2) will not guarantee to meet functional and AC specification if the operation temperature range out of range mentioned in above table. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 31 - W959D8NFYA 11.3.3 ICC Characteristics Parameter Description Test Conditions Min Typ*1 Max Unit ILI2 Input Leakage Current Reset Signal High Only VIN = VSS to VCC, VCC = VCC max – – 2 µA ILI4 Input Leakage Current Reset Signal Low Only *2 VIN = VSS to VCC, VCC = VCC max – – 15 µA ICC1 VCC Active Read Current (-40°C to +85°C) CS# = VIL, @200 MHz, VCC = VCC max – 16 24 mA CS# = VIL, @250 MHz, VCC = VCC max – 19 24 mA ICC2 VCC Active Write Current (-40°C to +85°C) CS# = VIL, @200 MHz, VCC = VCC max – 17 26 mA CS# = VIL, @250 MHz, VCC = VCC max – 20 26 mA ICC5 Reset Current CS# = VIH, RESET# = VIL, VCC = VCC max – – 1100 µA ICC6 Active Clock Stop Current (-40°C to +85°C) CS# = VIL, RESET# = VIH,VCC = VCC max – – 50 mA ICC7 VCC Current during power up*1 CS# = VIH, VCC = VCC max – – 70 mA IDPD Deep Power Down Current (85°C) CS# = VIH, VCC = VCC max – – 24 µA Parameter Description Min Typ*1 Max Unit Full Array – 170 2400 Bottom 1/2 Array – 140 1700 Bottom 1/4 Array – 130 1400 Bottom 1/8 Array – 120 1200 Top 1/2 Array – 140 1700 Top 1/4 Array – 130 1400 Top 1/8 Array – 120 1200 Full Array – 75 2200 Bottom 1/2 Array – 65 1600 Bottom 1/4 Array – 55 1200 Bottom 1/8 Array – 50 1000 Top 1/2 Array – 65 1600 Top 1/4 Array – 55 1200 Top 1/8 Array – 50 1000 ICC4 IHS VCC Standby Current (-40°C to +85°C) Hybrid Sleep Current (85°C) Test Conditions CS# = VIH, VCC = VCC max CS# = VIH, VCC = VCC max µA µA Notes: 1. Typical values are referring to the median average current measured @ TCASE=25°C and for reference only, not tested in mass production process. 2. RESET# Low initiates exits from DPD state and initiates the draw of ICC5 reset current, making ILI during Reset# Low insignificant. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 32 - W959D8NFYA 11.3.4 Power-Up Initialization HyperRAM products include an on-chip voltage sensor used to launch the power-up initialization process. VCC and VCCQ must be applied simultaneously. When the power supply reaches a stable level at or above VCC (min), the device will require tVCS time to complete its self-initialization process. The device must not be selected during power-up. CS# must follow the voltage applied on VCCQ until VCC (min) is reached during power-up, and then CS# must remain high for a further delay of tVCS. A simple pull-up resistor from VCCQ to Chip Select (CS#) can be used to insure safe and proper power-up. If RESET# is Low during power up, the device delays start of the tVCS period until RESET# is High. The tVCS period is used primarily to perform refresh operations on the DRAM array to initialize it. When initialization is complete, the device is ready for normal operation. VCC_VCCQ VCC Minimum tVCS CS# RESET# Figure 14 - Power-up with RESET# High VCC_VCCQ VCC Minimum CS# tVCS RESET# Figure 15 - Power-up with RESET# Low Table 16 - Power Up and Reset Parameters Parameter VCC tVCS Description VCC Power Supply VCC and VCCQ ≥ minimum and RESET# High to first access Min 1.7 Max 2.0 Unit V – 150 µS Notes: 1. Bus transactions (read and write) are not allowed during the power-up reset time (tVCS). 2. VCCQ must be the same voltage as VCC. 3. VCC ramp rate may be non-linear. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 33 - W959D8NFYA 11.3.5 Power-Down HyperRAM devices are considered to be powered-off when the array power supply (VCC) drops below the VCC LockOut voltage (VLKO). During a power supply transition down to the VSS level, VCCQ should remain less than or equal to VCC. At the VLKO level, the HyperRAM device will have lost configuration or array data. VCC must always be greater than or equal to VCCQ (VCC ≥ VCCQ). During Power-Down or voltage drops below VLKO, the array power supply voltages must also drop below V CC Reset (VRST) for a Power Down period (tPD) for the part to initialize correctly when the power supply again rises to V CC minimum. See Figure 16 - Power Down or Voltage Drop. If during a voltage drop the VCC stays above VLKO the part will stay initialized and will work correctly when VCC is again above VCC minimum. If VCC does not go below and remain below VRST for greater than tPD, then there is no assurance that the POR process will be performed. In this case, a hardware reset will be required ensure the HyperRAM device is properly initialized. VCC (Max) VCC VCC (Min) tVCS VLKO VRST tPD Time Figure 16 - Power Down or Voltage Drop The following section describes HyperRAM device dependent aspects of power down specifications. Table 17 - Power-Down Voltage and Timing Parameter Description Min Max Unit VCC VCC Power Supply 1.7 2.0 V VLKO VCC Lock-out below which re-initialization is required 1.5 – V VRST VCC Low Voltage needed to ensure initialization will occur 0.7 – V Duration of VCC ≤ VRST 50 – µS tPD Note: VCC ramp rate can be non-linear. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 34 - W959D8NFYA 11.3.6 Hardware Reset The RESET# input provides a hardware method of returning the device to the standby state. During tRPH the device will draw ICC5 current. If RESET# continues to be held Low beyond tRPH, the device draws CMOS standby current (ICC4). While RESET# is Low (during tRP), and during tRPH, bus transactions are not allowed. A Hardware Reset will: ◼ ◼ ◼ ◼ Cause the configuration registers to return to their default values Halt self-refresh operation while RESET# is low - memory array data is considered as invalid Force the device to exit the Hybrid Sleep state Force the device to exit the Deep Power Down state After RESET# returns High, the self-refresh operation will resume. Because self-refresh operation is stopped during RESET# Low, and the self-refresh row counter is reset to its default value, some rows may not be refreshed within the required array refresh interval per Table 12 - Distributed Refresh Interval per Temperature on page 25. This may result in the loss of DRAM array data during or immediately following a hardware reset. The host system should assume DRAM array data is lost after a hardware reset and reload any required data. tRP RESET# tRH tRPH CS# Figure 17 - Hardware Reset Timing Diagram Table 18 - Power Up and Reset Parameters Parameter Description Min Max Unit tRP RESET# Pulse Width 200 – nS tRH Time between RESET# (High) and CS# (Low) 200 – nS tRPH RESET# Low to CS# Low 400 – nS The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 35 - W959D8NFYA 11.3.7 Capacitance Characteristics Table 19 - Capacitive Characteristics Parameter Description Min Max Unit CI Input Capacitance (CK, CK#, CS#) 6.0 pF CID Delta Input Capacitance (CK, CK#) 0.25 pF CO Output Capacitance (RWDS) 6.0 pF CIO IO Capacitance (DQx) 6.0 pF CIOD IO Capacitance Delta (DQx) 0.25 pF Notes: 1. These values are guaranteed by design and are tested on a sample basis only. 2. These values are applies to die device only (does not include package capacitance). 3. Contact capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VCC, VCCQ are applied and all other signals (except the signal under test) floating. DQ’s should be in the high impedance state. 4. The capacitance values for the CK, CK#, RWDS and DQx signals must have similar capacitance values to allow for signal propagation time matching in the system. The capacitance value for CS# is not as critical because there are no critical timings between CS# going active (Low) and data being presented on the DQs bus. 11.4 Input Signal Overshoot During DC conditions, input or I/O signals should remain equal to or between V SS and VCC. During voltage transitions, inputs or I/Os may negative overshoot VSS to -1.0V or positive overshoot to VCC +1.0V, for periods up to 20 nS. VSSQ to VCCQ - 1.0V ≤ 20 ns Figure 18 - Maximum Negative Overshoot Waveform ≤ 20 ns VCCQ + 1.0V VSSQ to VCCQ Figure 19 - Maximum Positive Overshoot Waveform The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 36 - W959D8NFYA 12. TIMING SPECIFICATIONS The following section describes HyperRAM device dependent aspects of timing specifications. 12.1 Key to Switching Waveforms Valid_High_or_Low High_to_Low_Transition Low_to_High_Transition Invalid High_Impedance 12.2 AC Test Conditions Device under test CL Figure 20 - Test load reference Table 20 - Test Specification Description Output Load Capacitance, CL Minimum Input Rise and Fall Slew Rates Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels All 15 1.13 0-VCCQ VCCQ/2 VCCQ/2 Unit pF V/nS V V V Notes 1 2 2 Notes: 1. All AC timings assume this input slew rate. 2. Input and output timing is referenced to VCCQ/2 for single ended clock or RWDS or referenced to the crossing of CK/CK# for the differential clock pair. VCCQ Input VCCQ / 2 Measurement Level VCCQ / 2 Output VSS Figure 21 - Input Waveforms and Measurement Levels The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 37 - W959D8NFYA 12.3 AC Characteristics 12.3.1 Read Transactions Table 21 - HyperRAM Specific Read Timing Parameters 250 MHz Description 200 MHz 166 MHz 133 MHz Parameter Unit Min Max Min Max Min Max Min Max Chip Select High Between Transactions tCSHI 6 – 6 – 6 – 7.5 – nS HyperRAM Read-Write Recovery Time tRWR 35 – 35 – 36 – 37.5 – nS Chip Select Setup to next CK Rising Edge tCSS 4 – 4 – 3 – 3 – nS Data Strobe Valid tDSV – 5 – 5 – 12 – 12 nS Input Setup Time tIS 0.5 – 0.5 – 0.6 – 0.8 – nS Input Hold Time tIH 0.5 – 0.5 – 0.6 – 0.8 – nS HyperRAM Read Initial Access Time tACC 28 – 35 – 36 – 37.5 – nS Clock to DQs Low Z tDQLZ 0 – 0 – 0 – 0 – nS CK transition to DQ Valid tCKD 1 5 1 5 1 5.5 1 5.5 nS CK transition to DQ Invalid tCKDI 0 4.2 0 4.2 0 4.6 0 4.5 nS tDV 1 – 1.45 – 1.8 – 2.375 – nS CK transition to RWDS Valid tCKDS 1 5 1 5 1 5.5 1 5.5 nS RWDS transition to DQ Valid tDSS -0.4 0.4 -0.4 0.4 -0.45 0.45 -0.6 0.6 nS RWDS transition to DQ Invalid tDSH -0.4 0.4 -0.4 0.4 -0.45 0.45 -0.6 0.6 nS Chip Select Hold After CK Falling Edge tCSH 0 – 0 – 0 – 0 – nS Chip Select Inactive to RWDS High-Z tDSZ – 5 – 5 – 6 – 6 nS Chip Select Inactive to DQ High-Z tOZ – 5 – 5 – 6 – 6 nS HyperRAM Chip Select Maximum Low Time (TCASE < 85°C) tCSM – 4 – 4 – 4 – 4 µS Refresh Time tRFH 28 – 35 – 36 – 37.5 – nS tCKDSR 1 5.5 1 5.5 1 5.5 1 5.5 nS Data Valid (tDV min = tCKHP min - tCKD max + tCKDI max) CK transition to RWDS Low @CA phase @Read The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 38 - W959D8NFYA tCK tCKHP tCKHP CK# VIX(Max) VCCQ / 2 VIX(Min) CK Figure 22 - Clock Characteristics Table 22 - Clock Timings Description Parameter 250 MHz 200 MHz 166 MHz 133 MHz Unit Min Max Min Max Min Max Min Max tCK 4 100 5 100 6 100 7.5 100 nS CK Half Period - Duty Cycle tCKHP 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK Half Period at Frequency Min = 0.45 tCK Min Max = 0.55 tCK Min tCKHP 1.8 2.2 2.25 2.75 2.7 3.3 3.375 4.125 nS CK Period Notes: 1. Clock jitter of ±5% is permitted. 2. Minimum Frequency (Maximum tCK) is dependent upon maximum CS# Low time (tCSM), Initial Latency and Burst Length. 3. All parts list in order information table (section 2) will not guarantee to meet functional and AC specification if the t CK and tCKHP out of range mentioned in above table. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 39 - W959D8NFYA Table 23 - Clock AC/DC Electrical Characteristics Description Parameter Min Max Unit VIN -0.3 VCCQ + 0.3 V DC Input Differential Voltage VID(DC) VCCQ x 0.4 VCCQ + 0.6 V AC Input Differential Voltage VID(AC) VCCQ x 0.6 VCCQ + 0.6 V VIX VCCQ x 0.4 VCCQ x 0.6 V DC Input Voltage AC Differential Crossing Voltage Differential Clock Input Levels VCCQ+0.3V VIN MAX CK VCCQ/2 VIX VID(DC) VID(AC) CK# - 0.3V VIN MIN Notes: 1. CK and CK# input slew rate must be ≥1V/nS (2V/nS if measured differentially). 2. VID(DC) is the magnitude of the difference between the input level on CK and the input level on CK# when the CK and CK# is stable at a certain voltage level. 3. VID(AC) is the magnitude of the difference between the input level on CK and the input level on CK# when the CK and CK# is transient within a range defined for VIN. 4. The value of VIX is expected to equal VCCQ/2 of the transmitting device and must track variations in the DC level of V CCQ. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 40 - W959D8NFYA CS# tRWR = Read Write Recovery Additional Latency tACC = Access 4 cycle latency 1 4 cycle latency 2 CK#,CK tDSV RWDS tCKDSR tCKDS High = 2x Latency Count tCKD RWDS and Data are edge aligned DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 Command-Address Dn A Dn B Dn+1 A Dn+1 B Memory drives DQ[7:0] and RWDS Figure 23 - Read Timing Diagram — With Additional Latency Notes: 1. Timing parameters applicable to HyperBus. 2. Transactions must be initiated with CK = Low and CK# = High. 3. CS# must return High before a new transaction is initiated. 4. The memory drives RWDS during the entire Read transaction. 5. Transactions without additional latency count have RWDS Low during CA cycles. Transactions with additional latency count have RWDS High during CA cycles and RWDS returns low at tCKDSR. All other timing relationships are the same for both figures although they are not shown in the second figure. A four cycle latency is used for illustration purposes only. The required latency count is device and clock frequency dependent. 6. These parameters are required by HyperRAM. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 41 - W959D8NFYA CS# tCSH tCKHP tCSS CK CK# tDSZ tCKDS tOZ RWDS tDSS tCKD tDQLZ tCKDI tDV tCKD Dn A DQ[7:0] tDSH Dn B Dn+1 A Dn+1 B RWDS and Data are edge aligned and driven by the memory Figure 24 - Data Valid Timing Notes: 1. This figure shows a closer view of the data transfer portion of read transaction diagrams to more clearly show the Data Valid period as affected by clock jitter and clock to output delay uncertainty. 2. The tCKD and tCKDI timing parameters define the beginning and end position of the data valid period. 3. The tDSS and tDSH timing parameters define how early or late RWDS may transition relative to the transition of data. This is the potential skew between the clock to data delay t CKD, and clock to data strobe delay tCKDS. Aside from this skew, the tCKD, tCKDI, and tCKDS values track together (vary by the same ratio) because RWDS and Data are outputs from the same device under the same voltage and temperature conditions. 12.3.2 Write Transactions Table 24 - Write Timing Parameters Description Parameter 250 MHz 200 MHz 166 MHz 133 MHz Min Max Min Max Min Max Min Max Unit HyperRAM Read-Write Recovery Time tRWR 35 – 35 – 36 – 37.5 – nS HyperRAM Read Initial Access Time tACC 28 – 35 – 36 – 37.5 – nS Refresh Time tRFH 28 – 35 – 36 – 37.5 – nS HyperRAM Chip Select Maximum Low Time (TCASE < 85°C) tCSM – 4 – 4 – 4 – 4 µS RWDS Data Mask Valid tDMV 0 – 0 – 0 – 0 – nS The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 42 - W959D8NFYA CS# tRWR = Read Write Recovery Additional Latency tACC = Access CK#,CK 4 cycle latency 1 tDSZ RWDS DQ[7:0] 4 cycle latency 2 tDMV High = 2x Latency Count 47:40 39:32 31:24 23:16 15:8 Command-Address 7:0 CK and Data are center aligned Dn A Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and RWDS Figure 25 - Write Timing Diagram — With Additional Latency Notes: 1. Timing parameters applicable to HyperBus. 2. Transactions must be initiated with CK=Low and CK#=High. CS# must return High before a new transaction is initiated. 3. During write transactions with latency, RWDS is used as an additional latency indicator initially and is then used as a data mask during data transfer. 4. Transactions without additional latency count have RWDS Low during CA cycles and RWDS returns Hi-Z at tDSZ. Transactions with additional latency count have RWDS High during CA cycles and RWDS returns Hi-Z at tDSZ. All other timing relationships are the same for both figures although they are not shown in the second figure. A four cycle latency is used for illustration purposes only. The required latency count is device and clock frequency dependent. 5. At the end of Command-Address cycles the memory stops driving RWDS to allow the host HyperBus master to begin driving RWDS. The master must drive RWDS to a valid Low before the end of the initial latency to provide a data mask preamble period to the slave. This can be done during the last cycle of the initial latency. 6. The write transaction shown demonstrates the Dn A byte and the Dn+1 B byte being masked. Only Dn B byte and Dn+1 A byte are modified in the array. Dn A byte and Dn+1 B byte remain unchanged. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 43 - W959D8NFYA tCSHI tCSM CS# tCSH tCSS CK#,CK tDSV tDSZ RWDS tIS DQ[7:0] tIH CA [47:40] CA [39:32] CA [31:24] CA [23:16] CA [15:8] CA [7:0] RG [15:8] RG [7:0] Data Command-Address Figure 26 - Write Operation without Initial Latency (Register Write) Notes: 1. Transactions must be initiated with CK=Low and CK#=High. CS# must return High before a new transaction is initiated. 2. Writes without Initial Latency, do not have a turnaround period for RWDS. The slave device will always drive RWDS during the Command-Address period to indicate whether extended latency is required for a transaction that has initial latency. However, the RWDS is driven before the slave device has received the first byte of CA, that is, before the slave knows whether the transaction is a read or write, to memory space or register space. In the case of a write without Initial Latency, the RWDS state during the CA period does not affect the Latency of Register Write. Since master write data immediately follows the CommandAddress period in this case, the slave may continue to drive RWDS Low or may take RWDS to High-Z during write data transfer. The master must not drive RWDS during Register Write. Register Write do not use RWDS as a data mask function. All bytes of write data are written (full word writes). 12.3.3 Hybrid Sleep Timings Table 25 - Hybrid Sleep Timing Parameters Description Parameter Min Max Unit tHSIN – 3 µS CS# Pulse Width to Exit Hybrid Sleep tCSHS 60 3000 nS CS# Exit Hybrid Sleep to Standby wakeup time tEXTHS – 100 µS Min Max Unit Hybrid Sleep CR1[5]=1 register write to Hybrid Sleep power level 12.3.4 Deep Power down Timings Table 26 - Deep Power down Timing Parameters Description Parameter Deep Power Down CR0[15]=0 register write to DPD power level tDPDIN – 3 µS CS# Pulse Width to Exit DPD tCSDPD 200 3000 nS CS# Exit Deep Power Down to Standby wakeup time tEXTDPD – 150 µS The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 44 - W959D8NFYA 13. PACKAGE SPECIFICATION Package Outline TFBGA24 Ball (6x8 mm2 (5x5-1 ball arrays), Ball pitch: 1.00mm, Ø =0.40mm) A1 INDEX 3 2 A1 INDEX 1 1 A A B B C C D D E E 2 3 5 4 A e D1 SD 4 D 5 (24x PLACES) 0.15 M C A B e 0.08 M C SE E B E1 A1 C A A2 0.15 (4X) ccc C SEATING PLANE Controlling Dimensions are in milmeters DIMENSION SYM. DIMENSION Ball Land (inch) (mm) MIN. NOM. MAX. MIN. NOM. MAX. A --- --- 1.20 --- --- 0.047 A1 0.26 0.31 0.36 0.010 0.012 0.014 A2 --- 0.85 --- --- 0.033 --- b 0.35 0.40 0.45 0.014 0.016 0.018 D 7.90 8.00 8.10 0.311 0.315 0.319 D1 E 5.90 6.00 1 0.157 BSC 4.00 BSC 6.10 0.232 0.236 0.240 E1 4.00 BSC 0.157 BSC 0.039 TYP SE 1.00 TYP SD 1.00 TYP 0.039 TYP e 1.00 BSC 0.039 TBSC ccc --- --- 0.10 --- --- 0.0039 Ball Opening Note: 1. Ball land: 0.45mm. Ball opening: 0.35mm PCB Ball land suggested ≤ 0.35mm The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 45 - W959D8NFYA 14. REVISION HISTORY VERSION DATE PAGE A01-001 Jun. 04, 2021 All Initial formal datasheet 5 Refine RWDS Read Write Data Strobe description of section 4 32 Add ICC1 & ICC2 typical spec values 32 Revise Full Array of ICC4 & IHS typical spec values 32 Add 1/2, 1/4 & 1/8 Array of ICC4 & IHS typical spec values 32 Revise note #1 typical ICCX values definition A01-002 Nov. 09, 2021 38, 39, 42 DESCRIPTION Add 166 and133MHz AC parameters timing spec 38 Revise 250 and 200MHz tCKD min. spec values 38 Revise data valid calculation formula as below (tDV min = tCKHP min - tCKD max + tCKDI max) Note: The content of this document is subject to change without notice. The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Nov. 09, 2021 Revision: A01-002 - 46 -